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/Title (NB100LVEP221 - Clock Driver, HSTL/ECL/PECL, 2:1:20 Differential, 2.5V/3.3V)
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Acrobat Distiller 18.0 (Windows)
BroadVision, Inc.
2020-11-10T09:37:41+08:00
2019-01-09T16:23:50-07:00
2020-11-10T09:37:41+08:00
application/pdf
NB100LVEP221 - Clock Driver, HSTL/ECL/PECL, 2:1:20 Differential, 2.5V/3.3V
ON Semiconductor
The NB100LVEP221 is a low skew 2:1:20 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The two clock inputs are differential
ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The
LVPECL input signals can be either differential configuration or
single−ended (if the VBB output is used).
The LVEP221 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure tightest skew, both sides of differential outputs should be
terminated identically into 50 even if only one output is being used.
If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The NB100LVEP221, as with most other ECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows the
LVEP221 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies. For more information on PECL terminations, designers should
refer to Application Note AND8020/D.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single−ended LVPECL input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 F capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
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